Conventional memory chips generally comprise peripheral control logic and at least one memory array comprising a plurality of memory cells. In some chips, the memory control logic is coupled to the memory array via a translation circuit (e.g., a voltage converter). A translation circuit converts one fixed supply voltage from an external power supply to a different operating voltage suitable for the memory array. Typically, the memory cells operate at a minimum reliable operating voltage for storing and erasing information. In certain embodiments, the power supplies are each provided by an external power supply.
As illustrated in system 10 of FIG. 1A, a first fixed voltage VCC1 is provided to memory chip 12 from a power supply 50 on power supply line 55. The voltage VCC1 is provided on power rail 25 to logic circuitry in a peripheral region 20 of the chip 12, and to a voltage translation circuit (not shown) in translation region 30. The voltage translation circuit (e.g., a two-stage level-shifting circuit) is generally configured to increase or decrease the first voltage VCC1 to a second fixed voltage VCC2 from power rail 45 in memory array 40, where the voltage VCC2 on the power rail 45 is different from the voltage VCC1 in peripheral region 20. In certain conventional systems, the voltage VCC2 provided to memory array 40 is greater than that of the voltage VCC1 provided to peripheral circuit 20. The voltage VCC2 provided to the voltage translation circuit in the translation region 30 via voltage supply line 35 is generally the minimum reliable operating voltage at which the memory cells (not shown) in the memory array 40 can store and erase information. However, the typical two-stage translation circuitry in the translation region 30 introduces latency (e.g., the time to convert signals at the voltage VCC1 supplied to the peripheral region 20 to signals at the voltage VCC2 for the memory array).
FIG. 1B illustrates an alternative system 57 that includes a memory controller 70, a system power supply 50, a level shifter (L/S) 32, and memory chip 16. The system power supply 50 provides power to the memory controller 70. In such systems, the memory chip 16 may require a greater supply voltage than that provided by the system power supply 50. Level shifter 32 is located outside of the memory chip 16, between system control signal 72 (such as a read enable or write enable signal) from the memory controller 70 and input 18 to the memory chip 16. In some cases, more than one level shifter 32 is required. The level shifter(s) 32 consume significant board or system-on-chip (SOC) area and add significant delay, and are burdensome to the system designer as a result.
FIG. 1C illustrates a second conventional memory system 60 that utilizes a power supply 50 to provide power to a memory chip 14. Specifically, power supply 50 provides a fixed voltage VCC to both peripheral circuitry 22 and to memory array 42 through power supply line 65. Memory chip 14 is generally configured to operate at a voltage (e.g., VCC) greater than that of the minimum voltage required for the logic in the peripheral region 22 and/or for the cells (not shown) in the memory array 42 to retain data. As a result, the circuitry in the peripheral region 22 or the memory array 42 may operate at a voltage greater than its minimum required operating voltage. Operating circuitry at a voltage greater than the minimum required voltage increases power consumption and reduces the efficiency of the circuitry.
This “Background” section is provided for background information only. The statements in this “Background” are not an admission that the subject matter disclosed in this “Background” section constitutes prior art to the present disclosure, and no part of this “Background” section may be used as an admission that any part of this application, including this “Background” section, constitutes prior art to the present disclosure.